1. Field of the Invention
The present invention relates to a method for production of a semiconductor device.
2. Description of the Related Art
An existing method of producing a vertical transistor will be explained below with reference to FIGS. 2A to 2E.
As FIG. 2A shows, the first step is to work a semiconductor substrate 111 to form a source region 112 therein. Then the surface of the semiconductor substrate 111 is coated with a hard mask layer 113 which has a mask opening 114.
The semiconductor substrate 111 undergoes etching through the hard mask layer 113 as an etching mask. This etching forms a trench 115 which causes the source region 112 to appear at its bottom or gets into the source region 112.
As FIG. 2B shows, the hard mask layer 113 shown in FIG. 2A is removed and the inside of the trench 115 and the surface of the semiconductor surface 111 are coated with a gate insulating film 116, which is subsequently oxidized to form a silicon oxide film.
As FIG. 2C shows, the semiconductor substrate 111 is coated with a gate forming film 117 of polysilicon (to be made into a gate electrode) in such a way as to fill the inside of the trench 115, with the gate insulating film 116 interposed between them.
As FIG. 2D shows, the gate forming film 117 is made into a gate electrode 118 by ordinary lithography and etching through a resist mask, which is subsequently removed.
The gate electrode 118 is formed on the substrate 111 in such a way that it is wider than the trench 115.
The gate electrode 118 has its upper part covered with a side wall 119 by the ordinary side wall forming technique.
As FIG. 2E shows, the semiconductor substrate 111 has its upper part (adjacent to the gate electrode 118) converted into a drain region 120 for example by ion implantation with an impurity for conduction.
The silicide layer 121 is formed on the drain region 120. the silicide layer 121 is formed on the gate electrode 118. The drain region 120 and the gate electrode 118 are coated with a silicide layer 121 of cobalt or nickel silicide in the usual way. The way of forming the silicide layer 121 is the same as the way of forming an ordinary silicide layer.
In this way there is obtained the vertical transistor 101. (Japanese Patent Laid-open No. 2006-13556, hereinafter referred to as Patent Document 1.)
The vertical transistor 101 obtained as mentioned above is that the upper part of the gate electrode 118 extends over the semiconductor substrate 111. The extended part (numbered 118A) varies in length d as follows.
The extended part 118A formed by existing technologies greatly varies in length d due to mask misalignment in lithography. Such variation leads to fluctuation in transistor characteristics and prevents the scale down of transistors.
One way to control the length d of the extended part 118A is by self-alignment process which is described below. (See Patent Document 1.)
The self-alignment process consists of forming the trench 115, as explained above with reference to FIG. 2A, and performing wet etching or isotropic dry etching on the hard mask layer 113 so as to remove its portion close to the opening of the trench 115, as shown in FIG. 3. The removed portion 113S is where the extended part 118A of the gate electrode 118 is formed later. This process permits the extended part 118A, shown in FIG. 2E, to be self-aligned with the trench 115.
Dry etching, however, is liable to deteriorate transistor characteristics because it contaminates the channel region of the transistor with impurities originating from the etching gas or with foreign matter due to etching damage.
Wet etching is able to form the removed part 113S if the etchant is dilute hydrofluoric acid (DHF) and the trench 115 is formed by using a mask of silicon oxide (SiO2). However, it is limited in selective ratio because the mask is formed on an SiO2-based material such as STI (Shallow Trench Isolation) and LOCOS (Local Oxidation Of Silicon). In general, it is difficult to employ an SiO2-based material as an etching mask to form the trench.
The problem with selective ratio may be solved by using a silicon nitride film. However, the step of removing a portion of the hard mask layer 113 needs hot phosphoric acid which roughens the silicon surface, thereby deteriorating the transistor characteristics.
It follows, therefore, that the self-alignment process can be applied to form the extended part 118A of the gate electrode 118 with the possibility of deteriorating transistor characteristics.